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   Morse Code Translator (FPGA-Based Digital System)

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PROJECT OVERVIEW:
This project involved designing and implementing a Morse Code Display System on the Intel DE10-Lite FPGA board, written entirely in Verilog HDL.
The system converts English alphabets (A–Z) into their Morse-code equivalents, then visualizes and transmits them through both visual (LED blinking) and auditory feedback (mechanical relay clicks). The FPGA receives alphabetic input through onboard switches, encodes the signal using lookup logic, and generates precisely timed pulse sequencesrepresenting dots and dashes.
                           SYSTEM ARCHITECTURE  &  DESIGN:
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  • Modular Design in Verilog HDL: Each subsystem was implemented as an independent module (translateMorse, fsm, clk_xx, and morsedisplay) to ensure clear functional separation.

  • Clock Divider ( clk_xx ): Reduced the FPGA’s 50 MHz clock to 0.5 s intervals for accurate LED timing using a 25 million-cycle counter.

  • Finite State Machine (FSM): Controlled LED blinks and relay activation based on Morse sequence states and timing pulses.

  • translateMorse Module: Encoded each alphabet as dot/dash patterns (0 = dot, 1 = dash) with associated length registers for sequence control.

  • External Hardware Interface: LED and mechanical relay driven by a transistor amplifier circuit connected to the Arduino_IO12 pin, providing simultaneous light and sound feedback.

  • User Controls: SW[4:0] select letters; KEY[1] and KEY[0] start and reset transmission; HEX displays show alphabet and Morse translation.

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               MY ROLE AND LEARNING OUTCOMES: 

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I led the software architecture and Verilog development of this project, writing all major code modules, debugging FSM behavior, and ensuring clock synchronization across all subsystems. My contributions included:

  • Writing synchronous Verilog code for the FSM, clock divider, and lookup-based Morse encoder, ensuring cycle-accurate transitions between dot/dash states.

  • Implementing timing control logic to generate consistent 0.5 s pulses from the 50 MHz clock using counter-based clock division.

  • Developing the Morse translation logic that encoded 26 unique letters into variable-length binary sequences.

  • Performing functional simulation in Quartus Prime to validate timing diagrams, LED patterns, and state transitions before hardware upload.

  • Collaborating on final testing and hardware debugging with my teammate, who focused on relay interfacing and physical circuit stability.

Through this role, I gained hands-on expertise in synchronous logic design, Verilog FSM modeling, hardware-level debugging, and signal timing verification.

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   KEY TECHNICAL TAKEAWAYS:

  • Designed modular Verilog HDL architecture supporting state-machine-based digital control.

  • Implemented clock division and timing synchronization techniques for sequential signal generation.

  • Applied FSM principles for encoding–decoding processes in digital communication systems.

  • Learned to interface digital logic with electromechanical components (LED + relay).

  • Validated design using simulation and on-board testing, ensuring accurate state behavior under hardware constraints.

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